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Logical Structure
Logical Structure
Figure 1-3 Logical structure of the Atlas 800 inference server (model 3010)
Supports one or two Intel® Xeon® Scalable processors.
Supports 24 memory modules.
The processors interconnect with each other through two UltraPath Interconnect (UPI) buses at a speed of up to 10.4 GT/s.
Three PCIe riser cards connect to the processors through PCIe buses to provide ease of expandability and connection.
The RAID controller card on the mainboard connects to CPU 1 through PCIe buses, and connects to the drive backplane through SAS signal cables. A variety of drive backplanes are provided to support different local storage configurations.
The LBG-2 Platform Controller Hub (PCH) supports:
Two 10GE optical LOM ports or two 10GE electrical LOM ports
Two GE electrical LOM ports
Supports iBMC cards that use Huawei-developed management processor Hi1710. Such a card provides a Video Graphic Array (VGA) port, management network port, and debugging serial port.
Supports a maximum of seven AI accelerator cards, providing a maximum of 980 TOPS INT8 computing power.