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Logical Structure
Figure 1-3 Atlas 800 inference server (model 3010) logical structure
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- The server supports one or two Intel® Xeon® Scalable processors.
- The server supports up to 24 memory modules.
- The CPUs (processors) interconnect with each other through two UPI links at a speed of up to 10.4 GT/s.
- Three PCIe riser cards connect to the processors through PCIe buses to provide ease of expandability and connection.
- The RAID controller card on the mainboard connects to CPU 1 through PCIe buses, and connects to the drive backplane through SAS signal cables. A variety of drive backplanes are provided to support different local storage configurations.
- The LBG-2 Platform Controller Hub (PCH) supports:
- Two 10GE optical LOM ports or two 10GE electrical LOM ports
- Two GE electrical LOM ports
- The server uses Hi1710 management chip and supports a video graphic array (VGA) port, a management network port, and a debug serial port.
