CLOCK
- CLOCK/4/BITS_SWITCH
- CLOCK/4/BITS_SW_FR_IVLD
- CLOCK/4/CHIP_ERROR
- CLOCK/4/CHIP_RECOVER
- CLOCK/4/DCLS_LOS
- CLOCK/4/DCLS_RECOVER
- CLOCK/4/DSP_ERROR
- CLOCK/4/DSP_RECOVER
- CLOCK/4/FPGA_ERROR
- CLOCK/4/FPGA_RECOVER
- CLOCK/4/FRAMER_ERROR
- CLOCK/4/FRAMER_RECOVER
- CLOCK/4/FRAME_SRC
- CLOCK/4/FREQ_INSTANT_CHG
- CLOCK/4/FREQ_OFFSET
- CLOCK/4/FR_SW_FAIL
- CLOCK/4/FR_SW_RECOVER
- CLOCK/4/INT_PROC_COST
- CLOCK/4/LOCK_FAIL
- CLOCK/4/LOCK_SUCC
- CLOCK/4/OFFSET_ABNORMAL
- CLOCK/4/OFFSET_ADJUST
- CLOCK/4/OSC_25M_ERROR
- CLOCK/4/OSC_25M_RECOVER
- CLOCK/4/OSC_2M_ERROR
- CLOCK/4/OSC_2M_RECOVER
- CLOCK/4/OSC_388M_ERROR
- CLOCK/4/OSC_388M_RECOVER
- CLOCK/4/STOP_SLOT_SRC
- CLOCK/4/SYNC_BAD
- CLOCK/4/SYNC_FAIL
- CLOCK/4/SYNC_SUCC
- CLOCK/4/SYSTEM_SWITCH
- CLOCK/4/SYS_SW_FR_IVLD
- CLOCK/4/SYS_SW_INNER
- CLOCK/4/TIME_ADJUST
- CLOCK/4/TOD_LOCK_FAIL
- CLOCK/4/TOD_LOCK_SUCC
- CLOCK/4/TOD_LOS
- CLOCK/4/TOD_RECOVER
- CLOCK/4/TS_ABNORMAL
- CLOCK/4/TS_NOT_CHG
CLOCK/4/BITS_SWITCH
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] |
Indicates the number of BITS output interface. The values are as follows:
|
[STRING] |
Indicates the type of the clock source. The values are as follows:
|
CLOCK/4/BITS_SW_FR_IVLD
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] |
Indicates the number of BITS output interface. The values are as follows:
|
[STRING] |
Indicates the type of the clock source. The values are as follows:
|
CLOCK/4/DCLS_LOS
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] | Indicates the number of the BITS interface. The values are as follows: 0: BITS0 interface 1: BITS1 interface |
Possible Causes
1. The device where the BITS interface resides is faulty.
2. The cable connection between the BITS interface and the local device is abnormal.
Procedure
- Check whether the BITS interface is working normally by running the display clock self-test-result command to check whether the status of components including the E1/T1 framer and FPGA is normal.
- Check whether the link is normal.
- Check whether the BITS interface sends DCLS signal.
- Contact technical support personnel.
CLOCK/4/DCLS_RECOVER
CLOCK/4/DSP_ERROR
Procedure
- Restart the MPU to check whether the log persists.
- If not, the DSP program is not loaded normally.
- If so, the clock board is faulty.
- Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
CLOCK/4/FPGA_ERROR
Procedure
- Restart the MPU to check whether the log persists.
- If not, the FPGA is not loaded normally.
- If so, the clock board is faulty.
- Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
CLOCK/4/FRAME_SRC
Message
CLOCK/4/FRAME_SRC:[STRING] is selected as [STRING] to transmit clock signal to the clock board.
Description
An interface is selected as the clock source of left frame or right frame to transmit clock signal to the clock board.
CLOCK/4/FREQ_INSTANT_CHG
Description
The number of frequency changes is not 0. The log records the latest change and number of frequency changes.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[LONG] |
Indicates the latest frequency after change. |
[ULONG] |
Indicates the counter of frequency change. |
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- Run the display clock { bits0 | bits1 } command to view the BITS interface configuration. Check whether the clock configurations of upstream and downstream devices are correct, for example, whether bit/hz in the output mode of the upstream device is the same as that in the input mode of the local device.
- Check the frequent offset of the upstream clock source. Tools may be required.
- After the clock source is switched, if the log is generated on all interfaces of the local device, the local clock board may be faulty. Then perform an active/standby switchover on the clock boards.
- Record this log message and contact technical support personnel.
CLOCK/4/FREQ_OFFSET
Message
CLOCK/4/FREQ_OFFSET:The clock source [STRING] is selected as [STRING], and its frequency has offset. (LastPPM=[STRING], CurPPM=[STRING])
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the type of the clock source:
|
[STRING] |
Indicates the type of the clock source:
|
[STRING] |
Indicates the last frequency offset. |
[STRING] |
Indicates the current frequency offset. |
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- Run the display clock { bits0 | bits1 } command to view the BITS interface configuration. Check whether the clock configurations of upstream and downstream devices are correct, for example, whether bit/hz in the output mode of the upstream device is the same as that in the input mode of the local device.
- Check the frequent offset of the upstream clock source. The tool may be required.
- After the clock source is switched, if the log is generated on all interfaces of the local device, the local clock board may be faulty. Then perform an active/standby switchover on the clock boards.
- Record this log message and contact technical support personnel.
CLOCK/4/FR_SW_FAIL
Message
CLOCK/4/FR_SW_FAIL:The [STRING] clock source of forced switchover fails. (ClockSource=[STRING])
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the type of source selection:
|
[STRING] |
Indicates the type of the clock source:
|
Possible Causes
1: The clock source fails.
2: The offset of the clock source is large after the offset detection is enabled.
Procedure
- Check whether the upstream device works normally.
- Check whether the link is normal.
- Check whether the upstream device transmits clock signal.
- Run the display clock freq-deviation-detect-range command to view the frequency offset detection range. Check whether the frequency offset of the total received signal is large.
- Contact technical support personnel.
CLOCK/4/FR_SW_RECOVER
Message
CLOCK/4/FR_SW_RECOVER:The [STRING] clock source of force switch is restored. (ClockSource=[STRING])
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the type of source selection. The values are as follows:
|
[STRING] |
Indicates the type of the clock source. The values are as follows:
|
CLOCK/4/INT_PROC_COST
Message
CLOCK/4/INT_PROC_COST:The tick cost of processing clock interruption exceeds 100ms. (InterruptType=[ULONG], TickCost=[ULONG])
Description
If clock interruption duration exceeds 100 ms, an error may occur in software processing. This log is used to locate software design bugs.
Parameters
Parameter Name | Parameter Meaning |
---|---|
InterruptType |
Indicates the clock interruption type. |
TickCost |
Indicates the time spent on interruption processing. |
CLOCK/4/LOCK_FAIL
Possible Causes
1. The jitter of the traced clock source is high.
2. If the clock source is changed from the external clock source to the local clock source, this log is generated. It is normal.
Procedure
- Run the display clock mode command to check whether the traced time source is correct, and run the display clock source command to check whether the status of each time source is correct.
- If the preceding information is correct, Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
CLOCK/4/OFFSET_ABNORMAL
Message
CLOCK/4/OFFSET_ABNORMAL:The time offset is abnormal. (Up400nsCount=[ULONG], 200ns-400nsCount=[ULONG], 100ns-200nsCount=[ULONG], 50ns-100nsCount=[ULONG])
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] |
Indicates the number of times the time offset becomes greater than 400ns. |
[ULONG] |
Indicates the number of times the time offset is between 200ns and 400ns. |
[ULONG] |
Indicates the number of times the time offset is between 100ns and 200ns. |
[ULONG] |
Indicates the number of times the time offset is between 50ns and 100ns. |
Possible Causes
1. Generally, jitter occurs during the switchover of clock source. This log is generated when the jitter occurs.
2. The performance of the traced clock source degrades, for example, the time jitter occurs.
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- After the clock source is switched, if the log is generated on all the interfaces of the local device, the clock board of the local device may be faulty. Then perform an active/standby switchover. If the log does not occur, the original active clock board is faulty. You can replace the clock board.
- Record this log message and contact technical support personnel.
CLOCK/4/OFFSET_ADJUST
Message
CLOCK/4/OFFSET_ADJUST:The time offset is adjusted. (AbnormalOffset=[LONG], SendToLogicOffset=[LONG])
Description
The time offset is adjusted when the clock and time are locked. The log records the abnormal offset and offset sent to logic.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[LONG] |
Indicates the offset value. |
[LONG] |
Indicates the offset of the signal sent to the logic. |
Possible Causes
1. Generally, jitter occurs during the switchover of clock source. This log is generated when the jitter occurs.
2. The performance of the traced clock source degrades, for example, the time jitter occurs.
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- After the clock source is switched, if the log is generated on all the interfaces of the local device, the clock board of the local device may be faulty. Then perform an active/standby switchover. If the log does not occur, the original active clock board is faulty. You can replace the clock board.
- Record this log message and contact technical support personnel.
CLOCK/4/OSC_388M_ERROR
CLOCK/4/STOP_SLOT_SRC
Possible Causes
1. The clock source is switched to another slot according to the source selection rule.
2. The frame priority of the interface is deleted.
3. The interface becomes Down.
4. The interface is a 1000M electrical interface.
5. The interface is configured with loopback.
Procedure
- If the clock source is switched to another slot in the same frame, the log is normal.
- If the log is generated in other cases, do as follows:
- Run the display interface interface-type interface-number command to check whether the interface is in Down state. If so, rectify the fault to ensure that the interface is Up.
- Run the display interface interface-type interface-number command to check whether the interface is a 1000M electrical interface. The 1000M electrical interface does not support Ethernet synchronization. Do not use this type of interface.
- Check whether the loopback internal command is configured on the interface. If so, cancel the configuration.
- Check whether the interface has the frame priority configured using the clock priority command. If not, configure the frame priority for it.
- If the preceding information is correct, Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
CLOCK/4/SYNC_BAD
Description
Frequent offset of the clock source exceeds the threshold three consecutive times. This indicates that the clock synchronization fails.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the type of source selection. The
values are as follows:
|
[STRING] |
Indicates the type of the clock source. The
values are as follows:
|
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- Check whether the clock configurations of the upstream device and downstream device are correct and whether the output mode of the upstream device is the same as the input mode of the local device (bit/hz).
- Check the frequent offset of the upstream clock source. The tool may be required.
- After the clock source is switched, if the log is generated on all interfaces of the local device, the local clock board may be faulty. Then perform an active/standby switchover on the clock boards.
- Record this log message and contact technical support personnel.
CLOCK/4/SYNC_FAIL
Procedure
- Check whether the clock configurations of the upstream device and downstream device are correct and whether the output mode of the upstream device is the same as the input mode of the local device (bit/hz).
- Check the frequent offset of the upstream clock source. The tool may be required.
- After the clock source is switched, if the log is generated on all interfaces of the local device, the local clock board may be faulty. Then perform an active/standby switchover on the clock boards.
- Record this log message and contact technical support personnel.
CLOCK/4/SYSTEM_SWITCH
Message
CLOCK/4/SYSTEM_SWITCH:The system source selected switches from [STRING] to [STRING], and the system clock runs at [STRING] mode.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the type of the clock source. The values are as follows:
|
[STRING] |
Indicates the type of the clock source. The values are as follows:
|
[STRING] |
Indicates the operation mode of the clock. The values are as follows:
|
CLOCK/4/SYS_SW_FR_IVLD
Message
CLOCK/4/SYS_SW_FR_IVLD:The system source selected switches from the invalid source to [STRING], and the system clock runs at [STRING] mode.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the type of the clock source. The values are as follows:
|
[STRING] |
Indicates the operation mode of the clock. The values are as follows:
|
CLOCK/4/SYS_SW_INNER
Message
CLOCK/4/SYS_SW_INNER:The system source selected switches to 0: Inner clock, and the system clock runs at [STRING] mode.
Description
The clock source is switched from an external clock source to an internal clock source. The log records the operation mode of the system clock.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[STRING] |
Indicates the operation mode of the clock:
|
Possible Causes
1. The clock source is lost.
2. If the clock source is changed from the external clock source to the local clock source, this log is generated. It is normal.
Procedure
- Check whether the upstream device works normally.
- Check whether the link is normal.
- Check whether the upstream device transmits clock signal.
- Run the display clock freq-deviation-detect-range command to view the frequency offset detection range. Check whether the frequency offset of the total received signal is large.
- Contact technical support personnel.
CLOCK/4/TIME_ADJUST
Message
CLOCK/4/TIME_ADJUST:The time is adjusted. (DistinctAdjustCount=[ULONG], TinyAdjustCount=[ULONG])
Description
The clock board can perform distinct adjustment or fine tune on internal clock. This log is generated only when the clock board performs distinct adjustment. The log records the counts of distinct adjustment and fine tune.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] |
Indicates the distinct adjustment count. |
[ULONG] |
Indicates the tiny adjustment count. |
Possible Causes
1. Generally, jitter occurs during the switchover of clock source. This log is generated when the jitter occurs.
2. The performance of the traced clock source degrades, for example, the time jitter occurs.
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- After the clock source is switched, if the log is generated on all the interfaces of the local device, the clock board of the local device may be faulty. Then perform an active/standby switchover. If the log does not occur, the original active clock board is faulty. You can replace the clock board.
- Record this log message and contact technical support personnel.
CLOCK/4/TOD_LOCK_FAIL
Possible Causes
1. On the clock boards, the number of times the time stamp is adjusted exceeds a certain value.
2. If the time source is changed from the external time source to the local time source, this log is generated. It is normal.
Procedure
- Run the display clock mode command to check whether the traced time source is correct, and run the display clock source command to check whether the status of each time source is correct.
- If the preceding information is correct, Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
CLOCK/4/TOD_LOS
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] |
Indicates the number of the BITS interface:
|
Possible Causes
1. The device where the BITS interface resides is faulty.
2. The cable connection between the BITS interface and the local device is abnormal.
Procedure
- Run the display clock { bits0 | bits1 } command to check whether the BITS interface is working normally.
- Check whether the cable connection is normal.
- Check whether the BITS interface sends 1pps-tod signal.
- If the preceding information is correct, Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
CLOCK/4/TOD_RECOVER
CLOCK/4/TS_ABNORMAL
Description
Transient occurs in the time stamp received from the upstream device. The maximum phase discrimination is greater than 30 or the minimum phase discrimination is smaller than -30. The log records the maximum phase discrimination and the minimum phase discrimination.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[LONG] |
Indicates the maximum value of phase discrimination. |
[LONG] |
Indicates the minimum value of phase discrimination. |
Possible Causes
1. Generally, jitter occurs during the switchover of clock source. This log is generated when the jitter occurs.
2. The performance of the traced clock source degrades, for example, the time jitter occurs.
Procedure
- If the clock source is switched, this is a normal situation.
- If the clock source of the upstream device is switched, this is a normal situation.
- After the clock source is switched, if the log is generated on all the interfaces of the local device, the clock board of the local device may be faulty. Then perform an active/standby switchover. If the log does not occur, the original active clock board is faulty. You can replace the clock board.
- Record this log message and contact technical support personnel.
CLOCK/4/TS_NOT_CHG
Description
T1 time stamp or T2 time stamp received from the upstream device is not changed. The log records the number of times T1 and T2 time stamps are not changed.
Parameters
Parameter Name | Parameter Meaning |
---|---|
[ULONG] |
Indicates the number of unchanged T1 time stamps. |
[ULONG] |
Indicates the number of unchanged T2 time stamps. |
Possible Causes
1. An error occurs on the upstream interface that transmits signal. As a result, the time stamps are not updated.
2. The channel for receiving time stamps on the clock source is closed. As a result, the clock source cannot receive the updated time stamps.
Procedure
- Run the clock force source command to change the clock source and then check whether this log is generated on all interfaces of the local device.
- If so, the clock board of the local device is faulty. Perform an active/standby switchover of clock boards and go to step 2.
- If not, go to step 3.
- Check whether this log persists.
- If so, go to step 3.
- If not, the alarm handling ends.
- Collect log information and configuration information, and then contact technical support personnel. You can collect diagnostic information using the display diagnostic-information command.
- CLOCK/4/BITS_SWITCH
- CLOCK/4/BITS_SW_FR_IVLD
- CLOCK/4/CHIP_ERROR
- CLOCK/4/CHIP_RECOVER
- CLOCK/4/DCLS_LOS
- CLOCK/4/DCLS_RECOVER
- CLOCK/4/DSP_ERROR
- CLOCK/4/DSP_RECOVER
- CLOCK/4/FPGA_ERROR
- CLOCK/4/FPGA_RECOVER
- CLOCK/4/FRAMER_ERROR
- CLOCK/4/FRAMER_RECOVER
- CLOCK/4/FRAME_SRC
- CLOCK/4/FREQ_INSTANT_CHG
- CLOCK/4/FREQ_OFFSET
- CLOCK/4/FR_SW_FAIL
- CLOCK/4/FR_SW_RECOVER
- CLOCK/4/INT_PROC_COST
- CLOCK/4/LOCK_FAIL
- CLOCK/4/LOCK_SUCC
- CLOCK/4/OFFSET_ABNORMAL
- CLOCK/4/OFFSET_ADJUST
- CLOCK/4/OSC_25M_ERROR
- CLOCK/4/OSC_25M_RECOVER
- CLOCK/4/OSC_2M_ERROR
- CLOCK/4/OSC_2M_RECOVER
- CLOCK/4/OSC_388M_ERROR
- CLOCK/4/OSC_388M_RECOVER
- CLOCK/4/STOP_SLOT_SRC
- CLOCK/4/SYNC_BAD
- CLOCK/4/SYNC_FAIL
- CLOCK/4/SYNC_SUCC
- CLOCK/4/SYSTEM_SWITCH
- CLOCK/4/SYS_SW_FR_IVLD
- CLOCK/4/SYS_SW_INNER
- CLOCK/4/TIME_ADJUST
- CLOCK/4/TOD_LOCK_FAIL
- CLOCK/4/TOD_LOCK_SUCC
- CLOCK/4/TOD_LOS
- CLOCK/4/TOD_RECOVER
- CLOCK/4/TS_ABNORMAL
- CLOCK/4/TS_NOT_CHG