In the case of the TN11TBE, when the oversized and undersized packets synchronously enter the COS queue, the oversized packets are easier to be scheduled. Why?
The SP+DRR schedules the egress queues by bytes. When scheduling queues, the chip does not schedule packets section by section. Each queue is distributed with a credit counter according to the weight. When one schedule occurs, the value of the credit counter is decreased by one. The value of the credit counter can be lower than zero, which enables the schedule of entire oversized packets. In addition, one cell in the chip cannot be assigned with two schedule tasks. Thus, the cell utilization of the oversized packets is higher. As a result, the weight of the oversized packets at the egress is slightly higher than the theoretical value. Tests show that this scheduling offset is acceptable.