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Knowledge Base

Incorrect Configuration of the MST8000 Causes the Bit Errors in the Test of the OptiX OSN 1500

Publication Date:  2012-07-25  |   Views:  191  |   Downloads:  0  |   Author:  d00134946  |   Document ID:  EKB0000374922


Issue Description

A carrier uses the OptiX OSN 1500B. The SCC board is SSQ2CXL4. The SSN1PQ1 board is mounted in slots 12 and 13. The D75S interface board is mounted in slots 14 to 17. Use the MTS8000 to perform a 2M electrical interface bit error test for the equipment. The PQ1 board and the line board are cross-connected. Perform a hardware selfloop at the 2M electrical interface. In the test, bit errors occur in the MTS8000. Therefore, the OptiX OSN 1500B fails to pass the test. 

Alarm Information


Handling Process

1. Check the setting of the MTS8000 and find that the mapping structure of the packets is as follows: STM-4―>AU-4―>VC-12―>Bulk BERT―>Terminate. The clock source is Internal. The transmitted central wave length is 1310nm.
2. Change the mapping structure of the packets into: STM-4 ―> AU-4 ―> VC-12 ―>E1 BERT ―> Terminate .
3. Change the clock source to Recovered.
4. Perform a test again. The bit error test is passed, and the fault is rectified. 

Root Cause

1. Check the settings of the NMS and find that the configuration of the cross-connect is correct.
2. Perform internal loop for the software. Bit errors persist in the test.
3. The settings of the MTS8000 are incorrect. The settings are incorrect because the mapping structure of the packets is not correctly set. 


1. When you use the MTS8000 to perform a 2M bit error test on the NG SDH equipment, the clock source should be set to Recovered. On the SDH network, the clocks are synchronous. The clock signals of the MTS8000 should be extracted from the line of the SDH network. On the PDH network, the clock is plesiochronous. The clock source of the test instrument should be set to Internal.
2. In the mapping structure of the packets, the E1 BERT and Bulk BERT exist. The BERT means bit error rate testing. In the test, E1 and Bulk are two types of loads of VC12. VC-12 ―>E1 BERT means to perform a bit error test for the E1 signals. The VC12 is mapped by the E1 signals. VC-12 ―>Bulk BERT means to test the bit error rate when the load is bulk. The bulk, different form the E1 signals, is not divided into 32 time slots. In this test, the bit error rate of the 2M E1 electrical interface is tested. Therefore, the E1 BERT should be selected.